Electronic Design Automation (EDA) is used extensively in the design of integrated circuits. An electronic circuit under design is evaluated using models of devices and interconnections between the devices. A simulation using these models is then run to test the performance of the circuit.
Timing and signal integrity are ever increasingly important issues in integrated circuit design, particularly due to drastic scaling down rate of layout geometries as well as the increase in operating frequency. Static Timing Analysis (STA) method is used for verifying and analyzing the timing constraints for the circuit.
Variations in semiconductor processing of an integrated circuit can cause changes in its performance and yield. In nanometer technologies, the variations have become significant and can not be ignored. The process variations are variations in electric characteristics of transistors due to the upstream steps of producing the ICs on a wafer, or the downstream steps of sealing the IC chips produced in the upstream steps in various kinds of packages. The performance of a chip is also affected by environmental variations, such as variations in temperature or supply voltage. The fluctuations in production conditions also affect the shapes and physical conditions of circuit elements. Therefore, characteristic variations of the semiconductor integrated circuits are inevitable.
In conventional approaches, STA is performed at the transistor or cell level using libraries of information and characteristics such as delay and slew. Most of the conventional approaches are “vectorless” and avoid the expense of dynamic simulation (e.g., SPICE simulation) to estimate timing. Due to the phenomenal advancement in drawing extremely small transistor dimensions and the push for aggressive design styles to achieve better chip functionality, the voltage waveforms, commonly observed in modern chips may differ significantly from the assumptions of STA. Conventional static timing analysis tool are often unable to capture non-idealities in the waveforms, for example, overshoots, spikes, ringing, etc.
Additionally, it is often difficult to exhaustively characterize the cells for all possible loading conditions. Thus, approximate equivalent capacitance models are formed for interconnects to generate look-up table values for the gate models. Due to these approximations and the intrinsic limitations of the models, the generated output waveforms do not match the real circuit behavior. The problem is more severe in the case of non-linear loading conditions, such as when other gates are coupled to the output of the driver as fan-out gates. The problem is further exacerbated due to large changes in transistor and interconnects characteristics in the presence of process variations.
In summary, different kinds of variations have an effect on timing. It is desirable to consider semiconductor processing variations in performing a static timing analysis of an integrated circuit. Therefore, there is a need for a system and process to provide a STA tool for more accurate and fast calculations of timing analysis using distorted (noisy) output waveforms through gates and interconnects.